1. Field of the Invention
The present invention relates to an analog multiplier and more particularly, to a bipolar analog multiplier for multiplication of two analog signals that is formed on a semiconductor integrated circuit device and that can operate at a low voltage while enlarging the input voltage range providing a good linearity.
2. Description of the Prior Art
Conventionally, three types of bipolar multipliers were developed, analyzed and published by the inventor, K, Kimura. The first of them appeared in IEICE Paper of Technical Group on Circuits and Systems (CAS93-78), pp. 31-35, the second in the IEICE Transactions on Electronics, Vol. E76-C, No. 5, pp. 714-737 (pp. 735-736), and the third in Proceedings of the Engineering Sciences at the 1994 Society Conference of IEICE (A-11).
The conventional MOS multiplier disclosed in the above IEICE Paper of Technical Group on Circuits and Systems (CAS93-78) was further disclosed by K, Kimura, in IEEE Transactions on Circuits and Systems-I, Vol. 42, No. 8, pp. 448-454, August 1995, entitled "An MOS Four-Quadrant Analog Multiplier Based on the Multitail Technique Using a Quadritail Cell as a Multiplier Core". The conventional bipolar multiplier disclosed in the above IEICE Paper of Technical Group on Circuits and Systems (CAS93-78) was further disclosed by K, Kimura, in IEICE Transactions on Fundamentals, Vol. E78-A, No. 5, pp. 560-565, May 1995, entitled "A Bipolar Very Low-Voltage Multiplier Core Using a Quadritail Cell".
The inventor, K, Kimura, termed a circuit made of three or more transistors driven by a single (common) tail current a "multitail cell", and when the number of transistors is four, the circuit is termed a "quadritail cell".
These conventional multipliers will be described below. FIG. 1 shows a typical or basic configuration of the conventional bipolar multipliers.
In FIG. 1, the conventional multiplier has a quadritail circuit formed of four npn-type bipolar transistors Q51, Q52, Q53 and Q54 and a constant current source 51 (current value: I.sub.0) for driving the quadritail circuit. The transistors Q51, Q52, Q53 and Q54 have the same emitter area.
Emitters of the transistors Q51, Q52, Q53 and Q54 are coupled together. The constant current source 1 is connected between these coupled emitters and the ground. Collectors of the transistors Q51 and Q52 are coupled together. Collectors of the transistors Q53 and Q54 are coupled together.
Bases of the transistors Q51, Q52, Q53 and Q54 are applied with four input voltages V.sub.1, V.sub.2, V.sub.3 and V.sub.4, respectively. An output current I.sub.L is outputted from the coupled collectors of the transistors Q51 and. Q52. Another output current I.sub.R is outputted from the coupled collectors of the transistors Q53 and Q54. A differential output current .DELTA.I of the multiplier is defined as .DELTA.I=I.sub.L -I.sub.R.
In the multiplier of FIG. 1, if the relationship between the collector current the base-to-emitter voltage varies dependent on the exponent-law characteristic, the collector current I.sub.ci of the i-th transistor is expressed as the following equation (1), where I.sub.s is the saturation current, V.sub.BEi is the base-to-emitter voltage of the i-th transistor, and V.sub.T is the thermal voltage. ##EQU1##
The thermal voltage V.sub.T is expressed as V.sub.T =(kT)/q where k is Boltzmann's constant, T is absolute temperature in degrees Kelvin and q is the charge of an electron.
In the equation (1), if V.sub.BE is about 600 mV, the exponential term "exp (V.sub.BE /V.sub.T)" has a value in the order of e.sup.10, and therefore, the term "-1" can be neglected. As a result, the equation (1) can be approximated as the following equation (2). ##EQU2##
Then, assuming that all the transistors Q51, Q52, Q53 and Q54 are matched in characteristic, the collector currents of the transistors Q51, Q52, Q53 and Q54 driven by the tail current I.sub.0 are expressed as the following equations (3), (4), (5) and (6), respectively, where V.sub.R is the dc voltage of the input signals and V.sub.E is the common emitter voltage. ##EQU3##
Since the quadritail circuit in FIG. 1 is driven by the common tail current I.sub.0, the following equation (7) needs to be satisfied additionally, where .alpha..sub.F is the dc common-base current gain factor. EQU I.sub.C1 +I.sub.C2 +I.sub.C3 +I.sub.C4 =.alpha..sub.F I.sub.0( 7)
Solving the equations (3), (4), (5), (6) and (7) provides the following equation (8). ##EQU4##
The differential output current .DELTA.I is expressed as the following equation (9). ##EQU5##
It is seen from the equation (9) that the input voltages V.sub.1, V.sub.2, V.sub.3 and V.sub.4 needs to be adaptively decided in order to obtain the product of the input voltages in the differential output current .DELTA.I.
FIG. 2 shows an example of the conventional bipolar multiplier of FIG. 1, in which the input voltages V.sub.1, V.sub.2, V.sub.3 and V.sub.4 are adaptively set to linearire the differential output current .DELTA.I.
In the conventional multiplier of FIG. 2, a base of the transistor Q51 is applied with an input voltage (1/2)(V.sub.x +V.sub.y) with regard to a reference point. A base of the transistor Q52 is applied with an input voltage (-1/2)(V.sub.x +V.sub.y) with regard to the reference point. A base of the transistor Q53 is applied with an input voltage (1/2)(V.sub.x -V.sub.y) with regard to the reference point. A base of the transistor Q54 is applied with an input voltage (-1/2)(V.sub.x -V.sub.y) with regard to the reference point.
In the conventional multiplier of FIG. 2, since V.sub.1 =(1/2)(V.sub.x +V.sub.y), V.sub.2 =(-1/2)(V.sub.x +V.sub.y), V.sub.3 =(1/2)(V.sub.x -V.sub.y), and V.sub.4 =(-1/2)(V.sub.x -V.sub.y). Therefore, by substituting these into the equation (9), the differential output current .DELTA.I is expressed as the following equation (10). ##EQU6##
FIG. 3 shows another example of the conventional bipolar multiplier of FIG. 1, in which the input voltages V.sub.1, V.sub.2, V.sub.3 and V.sub.4 are adaptively set to linearize the differential output current .DELTA.I.
In this multiplier of FIG. 3, a base of the transistor Q51 is applied with an input voltage (1/2)V.sub.x with regard to a reference point (voltage: V.sub.R). A base of the transistor Q52 is applied with an input voltage [(-1/2)V.sub.x -V.sub.y ] with regard to the reference point. A base of the transistor Q53 is applied with an input voltage [(1/2)V.sub.x -V.sub.y ] with regard to the reference point. A base of the transistor Q54 is applied with an input voltage (-1/2)V.sub.x with regard to the reference point.
In the conventional muitiplier core circuit of FIG. 3, since V.sub.1 =(1/2)V.sub.x, V.sub.2 =(-1/2)V.sub.x -V.sub.y, V.sub.3 =(1/2)V.sub.x -V.sub.y, and V.sub.4 =(-1/2)V.sub.x, and therefore, the differential output current .DELTA.I is expressed as the following equation (11) from the equation (9). ##EQU7##
FIG. 4 shows further example of the conventional bipolar multiplier of FIG. 1, in which the input voltages V.sub.1, V.sub.2, V.sub.3 and V.sub.4 are adaptively set to linearize the differential output current .DELTA.I.
In this multiplier of FIG. 4, a base of the transistor Q51 is applied with an input voltage (V.sub.x +V.sub.y) with regard to a reference point. A base of the transistor Q52 is applied with an input voltage 0 (zero) with regard to the reference point. A base of the transistor Q53 is applied with an input voltage V.sub.x with regard to the reference point. A base of the transistor Q54 is applied with an input voltage V.sub.y with regard to the reference point.
In the conventional multiplier core circuit of FIG. 4, since V.sub.1 =V.sub.x +V.sub.y, V.sub.2 =0, V.sub.3 =V.sub.x, and V.sub.4 =V.sub.y, and therefore, the differential output current .DELTA.I is expressed as the following equation (12) from the equation (9). ##EQU8##
Thus, the equation (12) is the same as the equations (10) and (11).
FIG. 5 shows the input/output (or transfer) characteristic of the conventional multipliers of FIGS. 2, 3 and 4, and FIG. 6 shows the corresponding transconductance characteristic.
The right-hand side of the equation (10), (11) or (12) multiplied by .alpha..sub.F is equal to the differential output current of the well-known Gilbert multiplier cell.
An obtainable value of .alpha..sub.F through the typical bipolar processes is in the range from 0.98 to 0.99, which is extremely near 1. Therefore, it is seen from the equations (10), (11) and (12) that the conventional multipliers of FIGS. 2, 3 and 4 have the transfer characteristics approximately equal to that of the Gilbert multiplier cell.
Also, since the conventional multipliers of FIGS. 2, 3 and 4 do not contain the transistors stacked as in the Gilbert's one, they can operate at a lower voltage than the Gilbert's one.
The Gilbert multiplier cell can be linearized by incorporating the Gilbert gain cell, which is a well-known linearized circuit, in the input circuit, and the circuit thus created has originally been called the Gilbert multiplier.
The multiplier is an essential function block in analog signal processing. With the process of signal processing having become finer, the power supply voltage for LSIs has been decreased from 5 V to 3 V, or as low as 2 or 1 V, thus, a more advanced low-voltage circuit technology is increasingly been required. Such the conventional multipliers can originally be operated at a low voltage, however, as stated above, they have an input voltage range as narrow as that for the Gilbert multiplier cell. This causes a problem that only an extremely narrow range can be provided as a linear input voltage range.